A Skew-Window based Methodology for Timing Fixing in Multiple Power Modes

In the low power design of integrated circuits, multiple power modes and clock gating are the two common techniques to reduce dynamic power consumption. In the multiple power modes designs, replacing some of the normal buffers with adjustable delay buffers (ADBs) and assign different delay values in different power modes is one of the promising solutions to satisfy the clock skew constraint. On the other hand, when the clock gating technique is applied, usually gate splitting is necessary to satisfy the enable timing constraint. However, both ADBs insertion and gate splitting increase the hardware cost. In this paper, under both the enable timing constraint and clock skew constraint, we propose a skew-window based methodology to reduce the total hardware cost of ADBs and clock gates simultaneously. In comparison with when only ADBs insertion or gate splitting technique is applied, experimental results show that our methodology can satisfy the constraints in all the power modes and reduce the hardware cost effectively.